Chapter 7 Memory Basics
Memory Organization¶
- Access is based on words as the access unit.
Basic Memory Operations¶
- Read Memory
| Chip select | Read/not Write | memory operation |
| 0 | None | |
| 1 | 0 | Write to selected word |
| 1 | 1 | Read from selected word |
- Write Memory
Memory opertion timing¶
65ns -- 'read speed'--is critical for the whole speed.
RAM¶
Types of Random Access Memory¶
Static RAM -- Cell¶
Information stored in Latches
Select = 0 HOLD
Select = 1 OUTPUT DATA. 「INPUT depends on \(B\) and \(\bar{B}\)」
-
Bit select = 0 : NO WRITING or READING -- Bit Slice Disabled
-
Word select : only one allowed to be ONE
-
Bit select = 1:
| Read/not Write | B | not B | Word select | Result |
| 1 | 0 | 0 | 1 | One piece of information stored in one selected latch output |
| 0 | Data | not Data | 1 | The input information is stored in the one selected latch |
- \(2^{n-1}\) Word using 1-Bit RAM IC
Chip Select : When CS=0 Data Output 高阻态
Cell Arrays and Coincident Selection¶
- Uses two decoders, one for words and one for bits
- Word select becomes Row select
- Bit select becomes Column select
16x1
- Still one ONE chosen
RAM ICs with > 1 Bit/Word¶
8x2
Making Larger Memories: Word extension¶
Making Wider Memories: Bit extension¶
Dynamic RAM¶
information stored as electrical charges
- Read will affect the stored information(has to write again)
Read & Write¶
Types¶
Synchronous DRAM (SDRAM)¶
Transfers to and from the DRAM are synchronize with a clock
Synchronous registers appear on:
- Address input
- Data input
- Data output
Column address counter
- for addressing internal data to be transferred on each clock cycle
- beginning with the column address counts up to column address + burst size – 1
Example: Memory data path width: 1 word = 4 bytes
SDRAM burst time-- burst size=4
Double Data Rate SDRAM (DDR SDRAM)¶
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Transfers data on both edges of the clock
-
Provides a transfer rate of 2 data words perclock cycle
-
Example: Same as for synchronous DRAM
Read cycle time = 60 ns
Memory Bandwidth: (2 x 32)/(60 x 10-9) = 1.066 Mbytes/sec
- SRAM as Cache -- read more memory than expected makes CPU reads faster when asking for other data(CPU reads from SRAM)
SPEED UP!
RAMBUS® DRAM (RDRAM)¶
Dependence on Power Supply¶
Volatile¶
Loses stored information when power turned off
Non-volatile¶
Retains information when power turned off
创建日期: 2023年12月21日 20:26:54